copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. synchronous-rectifier pwm controller for pentium tm ii microprocessor features general description applications ? ? ? ? ? power supply for pentium tm , pentium pro tm , pentium tm ii,powerpc tm , k6 tm , 686 tm and alpha tm microprocessors ? ? ? ? ? high-power 5v to 3.xv (or below) dc-dc regu- lators ? ? ? ? ? low-voltage distributed power supplies the APW7004 provides a complete control and mul- tiple protection for a dc-dc converter optimized for high performance microprocessor applications. it is designed to drive two n-channel mosfets in a syn- chronous-rectified buck topology. the APW7004 in- tegrates output voltage control, output voltage programming, monitoring and protection functions into a single chip ic. the APW7004 includes a 5-bit digital-to-analog con- verter (dac) that provides a easily adjustable and precisely output voltage from 2.1v dc to 3.5v dc in 0. 1 increments and from 1.3 v dc to 2.05 v dc in 0. 05v increments. any selected output voltage can be maintained within 1% accuracy over temperature and line voltage variations. with a 200khz free-running triangle-wave oscillator and a error amplifier featuring a 15mhz unity-gain bandwidth and 6v/us slew rate inside the chip, APW7004 can implement a simple, single feedback loop, voltage-mode control topology with high tran- sient performance. the APW7004 also features with multiple protections against over-current and over-voltage conditions by inhibiting pwm operation. the APW7004 uses the r ds(on) of the upper mosfet as the current sensing element which eliminates the demend for an extra component. the APW7004 also monitors the output voltage using a comparator with hysteresis that tracks the dac output and issues a power good signal once the output is within 10%. 6 86 tm is a trademark of cyrix corporation alpha tm is a trademark of digital equipment corporation k6 tm is a trademark of advanced micro devices, inc. pentium tm is a trademark of intel corpora- tion powerpc tm is a trademark of ibm ? ? ? ? ? simple single-loop control design-voltage- mode pwm control ? ? ? ? ? fast transient response ? high-bandwidth error amplifier ? ? ? ? ? 5-bit digital-to-analog output voltage selec- tion ? wide range from1.3v dc to 3.5v dc ? 0.1v binary steps from 2.1v dc to 3.5v dc .05v binary steps from 1.3v dc to 2.05 v dc ? ? ? ? ? vid0-4 input pins with pull high resistors built in ? ? ? ? ? power-good output voltage monitor, pgood pin with an open collector configuration ? ? ? ? ? over-voltage and over-current fault monitors ? uses mosfet?s r ds(on) as current sensing, no extra element required ? ? ? ? ? programmable switching frequency setting ? 200khz free-running oscillator
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 2 pin description ordering information block diagram + - + - + - soft start + - + - + driver osc 110% 90% 115% v sen pgood cp2 cp2 cp2 ovp vid0 vid1 vid2 vid3 vid4 ttl d/a converer (dac) oc detn (power on reset) fb dac out comp detn (power on reset) rt erramp cp4 ss ugate lgate + - phase ocset cp1 ugate oc 200 a power on reset detn (power on reset) v cc ovp boot phase pgnd gnd 1 4 5 6 7 8 10 920 11 16 17 13 14 15 2 12 18 19 3 detn, oc APW7004 package code k : sop - 20 temp. range c : 0 to 70 c handling code tu : tube tr : tape & reel handling code temp. range package code v sen ocset ss vid0 ovp lgate pgnd boot vid1 vid2 vid3 vid4 comp fb v cc ugate phase pgood gnd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 17 18 19 20 rt
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 3 absolute maximum ratings symbol parameter rating unit v cc supply voltage 15 v v boot ?v phase boot voltage 15 v v i , v o input , output or i/o voltage gnd - 0.3 v to v cc + 0.3 v t a operating ambient temperature range 0 to 70 c t j junction temperature range 0 to 150 c t stg storage temperature range -65 to +150 c t s soldering temperature 300,10 seconds c electrical characteristics recommended operating conditions , unless otherwise noted thermal characteristics symbol parameter value unit r ja thermal resistance in free air sop sop (with 3in 2 of copper) 110 86 c/w APW7004 symbol parameter test conditions min. typ. max. unit v cc supply current i cc nominal supply ugate and lgate open 3 ma power-on reset rising v cc threshold vocset=4.5v 9.0 v falling v cc threshold vocset=4.5v 8.8 v oscillator free running frequency rt= open 185 200 215 khz ? v osc ramp amplitude rt= open 2 v p-p reference and dac dac(vid0-vid4) input low voltage 0.8 v dac(vid0-vid4) input high voltage 3.0 v dacout voltage accuracy -1.0 +1.0 % error amplifier dc gain 88 db gbw gain-bandwidth product 15 mhz sr slew rate comp=20pf 6 v/ s
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 4 APW7004 symbol parameter test conditions min. typ. max. unit gate drivers r ug, source upper gate source v boot- v phase =12v 8.3 ? r ug, sink upper gate sink v boot- v phase =12v 5 ? r lg, source lower gate source v cc =12v 8.3 ? r lg, sink lower gate sink v cc =12v 5 ? protection over-voltage trip (v sen /dacout) 115 120 % i ocset ocset current source v ocset =4.5v dc 170 200 230 a i ovp ovp souring current v sen =5.5v ,v ovp =0v 30 ma i ss soft start current 10 a power good upper threshold (v sen /dacout) v sen rising 110 % lower threshold (v sen /dacout) v sen rising 90 % hysteresis (v sen /dacout) upper and lower threshold 2% v pgood pgood voltage low i pgood = -5ma 0.5 v electrical characteristics cont. vsen (pin 1) connect this pin to the converter?s voltage output. the pgood and ovp comparator circuits monitor output voltage status and act over voltage protection by using this signal. ocset(pin 2) connect a resistor(r ocset ) from this pin to the drain of the upper mosfet. an internal 200ma current source (i ocs ), r ocset , and the upper mosfet?s on- resistance (r ds(on) ) set the converter over-current (oc) trip point according to the following equation: i peak = i ocs r ocset /r ds(on) an over-current trip resets the soft-start function. ss (pin 3) connect a capacitor from this pin to ground. this capacitor, along with an internal 10ma current source, pin function description sets the soft-start interval of the converter. vid0-4 (pins 4-8) vid0-4 are the input pins to the 5-bit dac. the states of these five pins decide the internal voltage refer- ence (dacout). the level of dacout sets the con- verter output voltage and also sets the pgood and ovp thresholds. table 1 specifies dacout for the 32 combinations of dac inputs. comp (pin 9) and fb (pin 10) comp and fb are the accessiable pins of the error amplifier. fb pin is the inverting input of the error amplifier and comp pin is output of the error amplifier. these pins provide the compensation for the volt- age-control feedback loop of the converter. gnd (pin 11) gnd is signal ground of the ic. all voltage levels are measured with respect to this pin.
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 5 electrical characteristics cont. pgood (piin 12) pgood is an open collector output used to indicate the status of the converter output voltage. this pin is pulled low when the converter output is not within 10% of the dacout reference voltage. the pgood pin is floating when no cpu exists. phase (pin 13) connect the phase pin to the source of the upper mosfet. this pin is used to monitor the voltage drop across the upper mosfet for over-current protection. ugate (pin 14) connect ugate to the upper mosfet gate. this pin enables the gate drive signal to drive the upper mosfet . boot (pin 15) boot pin provides bias voltage to the upper mosfet gate driver. a bootstrap circuit could be used to pump a boot voltage for enforcing the driv- ing capability of the gate driver and improving the performance of the upper mosfet. pgnd(pin 16) pgnd pin provides the power ground connection. connect this pin to the source of the lower mosfet. lgate (pin 17) connect lgate to the lower mosfet gate. this pin enables the gate drive signal to drive the lower mosfet. v cc (pin 18) connect v cc to 12v voltage supply. this pin sup- plies the bias for the chip. ovp (pin 19) ovp pin reports the event of an over-voltage condi- tion . converter output rising 15% more than the dac- set voltage triggers a high output on this pin with a typical 30ma sourcing capability which can be used to drive an external device and disables pwm gate drive circuitry. rt (pin 20) rt pin provides oscillator switching frequency adujstment. by connecting a resistor (r t ) from this pin to gnd, the nominal 200khz switching frequency is increased. conversely. connecting a pull-up re- sistor (r t ) from this pin to v cc reduces the switching frequency.
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 6 monitor and protection osc d/a + - + - pgood ss ovp rt vid0 vid1 vid2 vid3 vid4 fb comp v sen gnd pgnd lgate phase ugate ocset boot v cc v out APW7004 +12v v in = +5v application schematic table 1 output voltage program pin name pin name vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 0 1 1 1 1 1.3 11111 0 0 1 1 1 0 1.35 11110 2.1 0 1 1 0 1 1.4 11101 2.2 0 1 1 0 0 1.45 11100 2.3 0 1 0 1 1 1.5 11011 2.4 0 1 0 1 0 1.55 11010 2.5 0 1 0 0 1 1.6 11001 2.6 0 1 0 0 0 1.65 11000 2.7 0 0 1 1 1 1.7 10111 2.8 0 0 1 1 0 1.75 10110 2.9 0 0 1 0 1 1.8 10101 3.0 0 0 1 0 0 1.85 10100 3.1 0 0 0 1 1 1.90 10011 3.2 0 0 0 1 0 1.95 10010 3.3 0 0 0 0 1 2.00 10001 3.4 0 0 0 0 0 2.05 10000 3.5
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 7 packaging information so ? 300mil ( reference jedec registration ms-013) millimeters variations- d inches variations- d dim min. max. variations min. max. dim min. max. variations min. max. a2.35 2.65 so-16 10.10 10.50 a 0.093 0.1043 so-16 0.398 0.413 a1 0.10 0.30 so-18 11.35 11.76 a1 0.004 0.0120 so-18 0.447 0.463 b 0.33 0.51 so-20 12.60 13 b 0.013 0.020 so-20 0.496 0.512 d see variations so-24 15.20 15.60 d see variations so-24 0.599 0.614 e 7.40 7.60 so-28 17.70 18.11 e 0.2914 0.2992 so-28 0.697 0.713 e1.27bscso-14 8.80 9.20 e 0.050bsc so-14 0.347 0.362 h 10 10.65 h 0.394 0.419 l 0.40 1.27 l 0.016 0.050 n see variations n see variations 10 8 10 8 n 12 3 e h d l gauge plane 1 e b a1 a
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 8 reference jedec standard j-std-020a april 1999 reflow condition (ir/convection or vpr reflow) physical specifications pre-heat temperature 183 c peak temperature time temperature terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb) lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. packaging 1000 devices per reel classification reflow profiles convection or ir/ convection vpr average ramp-up rate(183 c to peak) 3 c/second max. 10 c /second max. preheat temperature 125 25 c) 120 seconds max temperature maintained above 183 c 60 ? 150 seconds time within 5 c of actual peak temperature 10 ?20 seconds 60 seconds peak temperature range 220 +5/-0 c or 235 +5/-0 c 215-219 c or 235 +5/-0 c ramp-down rate 6 c /second max. 10 c /second max. time 25 c to peak temperature 6 minutes max. package reflow conditions pkg. thickness 2.5mm and all bgas pkg. thickness < 2.5mm and pkg. volume 350 mm3 pkg. thickness < 2.5mm and pkg. volume < 350mm3 convection 220 +5/-0 c convection 235 +5/-0 c vpr 215-219 c vpr 235 +5/-0 c ir/convection 220 +5/-0 c ir/convection 235 +5/-0 c
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 9 reliability test program test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms , i tr > 100ma carrier tape & reel dimensions a j b t2 t1 c t ao e w po p ko bo d1 d f p1 application a b c j t1 t2 w p e sop-20 330 162 1.5 12.75 0.15 2 + 0.6 24.4 +0.2 2 0.2 24 + 0.3 - 0.1 12 0.1 1.75 0.1 application f d d1 po p1 ao bo ko t sop-20 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 8.2 0.1 13 0.1 2.5 0.1 0.35 0.013 (mm)
copyright ? anpec electronics corp. rev. p.4 - mar., 2001 APW7004 www.anpec.com.tw 10 cover tape dimensions carrier width 24 cover tape width 21.3 (mm) anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369 customer service
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